1. Field of the Invention
The present invention relates generally to the manufacturing of electronic assemblies, and more particularly to the manufacture of display devices.
2. Description of Related Art
Electronic assemblies such as display devices are known in the art. Display devices include a variety of displays such as field emission displays (FEDs), plasma display devices, and other suitable display devices. Each of these display devices are described below.
FEDs are generally used for television images, oscilloscope radar displays, computer displays, and other like applications. FIG. 1 illustrates a cross-sectional view of a FED known in the art. FEDs are comprised of anode 2 and cathode 8. Anode 2 comprises multiple layers of material. These multiple layers include a face layer 6, a vacuum layer 18, a conductive layer 20, and a luminescent layer 22. As noted in U.S. Pat. No. 5,818,165, the face layer 6 of the anode 2 may be comprised of flexible material.
Face layer 6 has a top and bottom surface. The bottom surface of face layer 6 is parallel to cathode 8. Face layer 6 must be comprised of material that allows the face layer 6 to have sufficient strength to maintain a vacuum. Vacuum layer 18 is introduced onto the bottom side of face layer 6. Vacuum layer 18 also has a top and bottom side. The top side of vacuum layer 18 is adjacent to face layer 6. Vacuum layer 18 may be comprised of a flexible material such as silicon dioxide (SiO2), silicon nitride (Si3N4), or silicon carbide (SiC).
Conductive layer 20 is formed onto the bottom surface of the vacuum layer 18. Conductive layer 20 may be approximately 1500 Å thick and comprised of indium tin oxide or other conductive material. Luminescent layer 22 is formed onto the bottom surface of conductive layer 20. The luminescent material may be comprised of phosphorous (P) or other luminescent material.
Cathode 8 is parallel to the anode 2. Cathode 8 is also comprised of multiple layers. Cathode 8 has a backing layer 10, a plurality of conductors 12, a resistive layer 24, insulating layer 28, and a gate electrode layer 26. Backing layer 10 may be comprised of a flexible metal layer such as aluminum laminated to a flexible insulating layer 28.
Conductors 12 are located on the interior of the backing layer 10. Conductors 12 includes conductive material such as nibium (Nb), aluminum (Al), or other like elements. Conductors 12, approximately 2,000 Å thick, may be parallel strips that intersect at right angles.
Resistive layer 24 includes resistive material such as silicon (Si) or silicon compounds, is formed on conductors 12 and backing layer 10. The resistive layer may be 10,000 Å–12,000 Å thick. Insulating layer 28 is deposited on top of the resistive layer 24 and may be comprised of silicon dioxide (SiO2). Insulating layer 28 may be 1.0–1.2 μm thick. Gate electrode layer 26, formed on top of the insulating layer 28, may be comprised of Nb and have a thickness of 2,000 Å. Gate electrode layer 26 may be formed through physical deposition (e.g. sputtering, evaporation, etc.) onto the insulating layer, chemical vapor deposition, or the like.
A gap 917 of approximately 200 μm exists between the anode 2 and the cathode 8. This gap may be created by inserting a nonconductive layer of approximately the thickness of the gap. A flexible frit 30 may include a material such as glass fibers bound together with epoxy materials is formed between anode 2 and cathode 8.
Spacer 921 supports the display against the atmospheric pressure and allows the display area to grow without increasing the thickness of either the anode or the cathode. To seal anode 2 and cathode 8, the device described above undergoes an annealing process. The annealing process operates at a temperature that causes the epoxy material to melt away. Flexible layer 16 is wrapped over the insulating layer 28 creating a vacuum seal with flexible frit 30. The vacuum or negative pressure in the gap is maintained by flexible frit 30, flexible layer 16, and vacuum layer 18 that is disposed completely around the periphery of the display 1.
A picture is created on a FED having an anode which has a transparent conductive material coating on a transparent display screen. When the electrons collide with the screen, the point of collision forms all or part of a picture element (e.g., pixel) of a displayed image. The higher the rate of collision of electrons with the anode 2, the greater the brightness of the pixel.
FEDs have either active or passive matrix panels. Active and passive matrix panels may be transmissive. Transmissive displays include polysilicon thin-film transistor (TFT) displays and high-resolution polysilicon displays.
FIG. 2 is a schematic diagram of a portion of a passive matrix FED that includes rows 36A–36C of extraction grids and columns 34A–34C of emitters 913. The emitters 913 emit electrons when an appropriate voltage is applied to a row 36A–36C and a column 34A–34C. The shift register 301 receives a horizontal synchronization signal that activates buffers 32A–32C. Buffers 32A–32C provide a grid voltage from a grid voltage generator 31 to rows 36A–36C of the extraction grid. Emitter drive currents are generated by circuits 38A–38C. The emitter drive currents are proportional to the luminance signals to the columns 34A–34C.
FIG. 3 is a schematic diagram of a portion of an active matrix FED. An emitter drive circuit 44 is created by a pair of negative-channel metal oxide semiconductor (NMOS) transistors 40 and 42 together with a resistor that is serially coupled between the emitters 46. FED 50 has one continuous extraction grid 48 that is generally active on a continuous basis when the FED 50 is in use. Emitters 46 are activated by an enable signal that is applied to the gate of transistor 40 in which the transistor 40 acts as a closed switch.
FIG. 4 illustrates a conventional emitter 14. Generally, emitters 14 are cone-shaped where the top of the cone is thinner than the bottom of the cone shape. Emitters 14 may be comprised of conductive material such as molybodenum (Mo) or other suitable material. When an emitter 14 is excited, electrons are emitted from the tip of the emitter which occurs when an enable signal is applied to the gate of a transistor.
FIG. 5 illustrates a cross-sectional view of a FED of the prior art. FEDs have a substrate that has recessed regions for emitters. Spacers are used to separate the anode from the cathode. Phosphor dots are parallel to the substrate. Black matrix is interspersed between the spacers and the phosphor dots.
FIG. 6 illustrates a cross-sectional view of a FED of the prior art. Anode 2 is parallel to cathode 903. Gates are located between emitters. A frit seal 909 is connected to anode 2 and cathode 903. External column driver chip is coupled to the substrate used for cathode 903. Red, green, and blue phosphor dots 70 are parallel to the emitters.
Fabrication of plasma displays is well known in the art and is generally described in U.S. Pat. No. 5,844,373. Plasma displays are typically used for advertisements, portable computers, or any other type of displays that require a large screen size.
As shown in FIG. 7, a plasma display typically comprises a cell such as a liquid crystal cell 901, a plasma cell 4, and a dielectric layer 905 interposed between them. Dielectric layer 905 is thin for driving the liquid crystal cell 901, and a thin plate glass with a thickness of about 50 μm surrounds the dielectric layer 905. The liquid crystal cell 901 includes a substrate 8A that is comprised of glass and electrode 12 that are in the main inner surface of the substrate 8A. Substrate 8A is coupled to the dielectric layer 905. Gap 911 is created using spacers 24. Liquid crystal material fills gap 106.
Plasma cell 4 includes a substrate 22 that is typically comprised of glass and a plurality of electrodes (also referred to as rods) 18 are formed in a stripe pattern on the main surface of the substrate 22. Gap 911 exists between the dielectric layer 905 and substrate 22. Gap 911 is created between dielectric layer 905 and substrate 22 by barrier ribs 907 and frit seals 909 as illustrated in FIG. 9. Barrier ribs 907 are usually 100 to 300 μm in height and 100 μm width. Although barrier ribs 907 are shown on top plasma electrodes, barrier ribs 907 may be spaced apart and not be contacted with the plasma electrodes or barrier ribs 907 may be formed apart from the plasma substrate glass such as on the dielectric layer 905. Frit seals 909 are typically comprised of a low melting glass. An ionizable gas such as helium, neon, argon, xenon or a mixture thereof is sealed in the space created by barrier ribs 907 and frit seal 909. Barrier ribs 907, formed on each of the plasma electrodes by a means such as screen printing process, create space for the plasma cell. Plasma cell 4 is divided by the barrier ribs 907 into stripe portions that constitute electric discharge channels.
Plasma displays create an image based upon the principle that an electrical discharge in an inert gas causes luminescence. A surface discharge display panel has fluorescent material that emit light when excited by ultraviolet light. As voltage is applied sequentially to scanning electrodes, lines on the display screen are selected one by one. In conjunction with the selection of lines, three data electrodes intersect the line that is selected. Because the three data electrodes correspond to primary colors of light such as red, green, and blue, a picture element (e.g. a pixel) is formed on the display screen. A picture element is created when the discharge channel and the signal electrode D intersect.
Three voltages are generally required to form and maintain a display of a plasma display panel: (1) a voltage Va of approximately 50 volts is typically applied to data electrodes; (2) voltage Vs of approximately 180 volts is required for maintaining discharge is applied to the sustaining electrodes; and (3) an entire surface discharge sustaining voltage Vd of approximately 330 volts.
Plasma electrodes 12 act alternately as an anode and a cathode to generate a plasma discharge. The discharge is substantially defined by barrier ribs 907.
As shown in FIG. 8, display electrodes and data electrodes are disposed on the front plate and the base plate. These display electrodes are comprised of discharge scanning electrodes. As mentioned above, while voltage is applied to the discharge sustaining electrodes, lines on the display screen are selected one by one. Three data electrodes correspond to three primary colors such as red (R), green (G), and blue (B). Three points (R, G, B) where the data electrodes intersect the line that is selected by discharge sustaining electrodes and composes a pixel element (e.g. pixel) on the display screen.
Voltage of approximately 50 volts is required for starting a discharge and is applied to the data electrodes. Maintaining the discharge requires a voltage of approximately 180 volts to be applied to both the discharge sustaining and scanning electrodes. Approximately 330 volts is applied to the discharge sustaining electrodes to start a discharge over the entire surface of the display panel (hereinafter referred to as entire-surface discharge). The display panel, therefore, requires a data selection voltage of approximately 50 volts, an entire-surface-discharge-starting voltage of approximately 330 volts, and a discharge-sustaining voltage of approximately 330 volts.
The display is created when voltage is applied to the sustaining electrodes in the entire surface discharge and a ground is applied sequentially to the discharge scanning electrodes, lines are scanned and selected one after another. The data electrodes are driven according to the display data to be displayed on the line, the display cells on the selected line discharge and display the display data. Reading of the display data for each display cell from the I/O buffers drivers the data electrodes. The display cell discharges or does not discharge depending upon whether voltage or ground is applied to the data electrodes.
As shown in FIG. 9, a plasma display has a liquid crystal cell coupled to a dielectric sheet. The liquid crystal cell has a uniformly thin sheet of glass that is approximately 50 μm. The dielectric sheet is also coupled to a plasma cell. The plasma cell is surrounded by an uniformly thin sheet of glass that is approximately 50 μm.
These plates are parallel to each other and are typically comprised of glass. The two glass plates of a plasma display are separated by spacers and sealed and evacuated. One of the glass plates (e.g., face plate) has a screen that has light-emitting material on it or under it, such as plasma, a phosphor, or a color filter or other medium.
FIG. 10 illustrates a rod 14A and a circuit element 18 on the top surface of a cylindrical rod 14A. These rods may take a variety of shapes but they are generally elongated and rectangular in shape.
FIG. 11 illustrates a portion of an array in an active matrix display backplane for a plasma display. Plasma displays may have an alternate type of active matrix liquid crystal array. The control line rows in this device are coupled to gate electrodes along a row and the control line columns are coupled to data drivers which supply pixel voltages which are applied to the pixel electrodes. A column line 34 is connected to a source electrode of field effect transistor (FET). Another column line is coupled to a source electrode of FET. A row line 32 is coupled to the gates of both FETs 36 and 37. The drain of FET 36 is coupled through capacitor 923 to a transparent pixel electrode along the row 32 formed by FETs 36 and 37, and the drain of FET 37 is coupled through a capacitor to another pixel electrode along the row. In one typical example, the backplane may be formed by depositing rods using an FSA technique into a rigid substrate (e.g., glass). Each rod contains a FET and a capacitor and is interconnected to other rods by column and row conductors that are deposited onto the rigid substrate; and, the capacitor is coupled to a pixel electrode by another conductor that is deposited onto the rigid substrate. The active medium (e.g., plasma) is placed between the base and face plates which will optically change the active medium's properties in response to the combined voltages or currents produced by the pixel electrodes. The active medium at a given pixel electrode 42 will appear as a square or dot in the overall checkerboard type matrix of the display. The actual size of the FETs and the pixel electrodes are not now drawn to scale, but are shown schematically for the purposes of illustration. The interconnect (e.g., rods) between the rows and columns is comprised of flexible and conductive material. For example, the interconnect could be made of aluminum, copper, gold or other conductive materials.
A circuit using a complimentary metal oxide semiconductor (CMOS) technology (not shown) and a diffused metal on silicon (DMOS) transistor are also used in a plasma display. CMOS is used for illumination and pulse control and generally relates to linking a PMOS (a semiconductor doped with a p-type dopant) transistor device with an NMOS (a semiconductor doped with n-type dopant) device. CMOS is used outside of the array. DMOS is used for high power plasma displays.
There are several disadvantages inherent to display devices such as FEDs. For example, the FED described in U.S. Pat. No. 5,818,165 discloses a FED in which the plurality of emitters and gates are created on one layer of the cathode of the FED. This is inefficient because a portion of the emitters will be inoperable. Additionally, FEDs are typically manufactured by using deterministic methods to place driver chips and spacers onto one of the layers of the cathode. This reduces productivity because it is more efficient to use a method in which premanufactured objects are quickly placed onto a layer.
Another disadvantage to existing FEDs is that they are typically manufactured in a batch operation. Batch operations inherently involve a certain amount of down-time in production. This increases aggregate production time to fabricate display panels. Moreover, flat-panel displays are generally fabricated on substrates which are not continuous in length. This also decreases productivity since the assembly of the flat-panel displays is interrupted until another panel is available to assemble the flat-panel display.
There are also several disadvantages associated with conventional plasma displays. For example, plasma displays are also manufactured using deterministic methods with regard to placing rods onto one of the glass plates such as the base plate. This reduces productivity because it is more efficient to use a method in which objects are quickly placed onto the rigid substrate, such as through fluidic self assembly. Another disadvantage to plasma displays is that they are also typically manufactured in a batch operation. It is therefore desirable to have a method of manufacturing display devices such as FEDs and plasma displays that overcome the disadvantages associated with conventional display device.